The present invention relates to a semiconductor memory circuit, and particularly to a data read circuit for a Read Only Memory (hereafter referred to as ROM).
This application is a counterpart application of Japanese application Ser. No. 213610/2000, filed Jul. 14, 2000, the subject matter of which is incorporated herein by reference.
A plurality of memory cells constituting a memory cell array of a conventional ROM circuit are made using, for example, non-volatile MOS (Metal Oxide Semiconductor) transistors such as MOS transistors having a floating gate electrode. Drain electrodes of MOS transistors making up these plurality of memory cells are connected to select lines, while source electrodes are connected to bit lines. The select lines and the bit lines are arranged alternately, to form a plurality of column lines. Also, a control gate electrode (control gate) of each MOS transistor is connected to a plurality of word lines making up a row line.
Next, a data write operation for a memory cell of a ROM circuit such as that described will now be described. Of the above described column lines, each select line connected to a drain electrode of a MOS transistor is connected to a drain power supply circuit through a select line selection transistor. This drain power supply circuit supplies a voltage of, for example, 4.5 V to a selected select line when data is written to a memory cell. On the other hand, each of the bit lines connected to a source electrode of a MOS transistor is connected to a data write circuit through a bit line selection transistor. This data write circuit supplies a ground potential to a selected bit line when data of xe2x80x9c0xe2x80x9d is written to a memory cell (electrons are injected into the floating gate of the MOS transistor constituting the memory cell), and supplies a voltage of, for example, 3V to the selected bit line when data of xe2x80x9c1xe2x80x9d is written to the memory cell (electrons are not injected into the floating gate electrode of the MOS transistor constituting the memory cell). During the data write operation, a voltage of, for example about 8 V is applied to the word line connected to the memory cell subject to data write, and the select line selection transistor and bit line selection transistor connected to the same memory cell are put into a conducting state. When a voltage of 4.5 V is applied between the drain electrode and source electrode of a MOS transistor constituting the memory cell, data of xe2x80x9c0xe2x80x9d is written into the memory cell, while when a voltage less than 1.5 V is applied, data of xe2x80x9c1xe2x80x9d is written to the memory cell.
After that, for the data cell to which data has been written, a verify operation is performed to confirm that the desired data has been written, in which the potential of the select line and the word line are set to ground potential by the drain electrode power supply and the data write circuit as the potential of the word line is lowered. By carrying out this kind of 1:1 operation, for example, it is confirmed whether or not an erroneous data write has occurred to the memory cell due to residual charge on the bit line.
As described above, in a conventional ROM circuit, for example, when an operation to write data of xe2x80x9c1xe2x80x9d into the memory cell is started or completed, a voltage applied to the source electrode and drain electrode of the MOS transistor constituting the memory cell is raised or lowered by a separate circuit, namely the drain electrode power supply and the write circuit.
However, in the case of such a data xe2x80x9c1xe2x80x9d write operation, there is a possibility of erroneous data being written to the memory cell due to either the voltage applied to the source electrode being higher than the voltage applied to the drain electrode when the voltage is raised, or the difference in voltage between the voltage applied to the source electrode and the voltage applied to the drain electrode being too large (for example a difference greater than 1.5 V) when the voltage is lowered.
To suppress such erroneous data writes, there has been considered a method where, in the case of commencing a data xe2x80x9c1xe2x80x9d write operation, the supply of voltage to the word line is only commenced after the voltage applied to the drain electrode and source electrode of the MOS transistor constituting the memory cell has become sufficiently stable, or after the voltage applied to the drain electrode has become higher than the voltage applied to the source electrode. On the other hand, in the case of completing a data xe2x80x9c1xe2x80x9d write operation, there has been considered a method of lowering the potential of the word line before a difference between the voltage applied to the drain electrode and the source applied to the electrode becomes large.
However, when such a data xe2x80x9c1xe2x80x9d operation is commenced, if there is a delay in commencing supply of voltage to the word line the time required to write data xe2x80x9c1xe2x80x9d to the memory cell is a increased. Also, when completing the data xe2x80x9c1xe2x80x9d write operation, if the lowering of the voltage to the word line is early the data write to the memory cell is insufficiently carried out, with the result that there is a possibility of an erroneous data write occurring.
Accordingly, in the ROM circuit it is preferable on the one hand to prevent any increase in the time required to write data of xe2x80x9c1xe2x80x9d to the memory cell as described above, and on the other hand to effectively prevent the possibility of write errors when commencing or completing data xe2x80x9c1xe2x80x9d write to the memory cell.
An object of the present invention is to provide a semiconductor memory circuit capable of effectively suppressing write errors while also preventing an increase in the time taken to perform a data write to a memory cell.
In order to achieve the above described object, a semiconductor storage device of the present invention comprises a plurality of select lines and bit lines arranged alternately, a plurality of word lines arranged substantially orthogonal to the select lines and bit lines, a plurality of MOS transistors, having first electrodes connected to the select lines, second electrodes connected to the bit lines and control electrodes connected to the word lines, forming a plurality of memory cells, a first voltage supply circuit connected to the select lines for supplying a first voltage to the first electrodes, and a second voltage supply circuit connected to the bit lines and the select lines for supplying a second voltage, varying in compliance with variation in the first voltage, to the second electrodes.